In order to increase the gate density and operating speed of integrated circuits, the feature size of transistors within the circuit must decrease. In conventional fabrication processes the creation of source/drain regions by diffusion results in some amount of lateral diffusion beneath the gate region. The amount of lateral diffusion under the gate area can be limited to some extent by use of oxide spacers. However the lateral diffusion must also generally be limited by controlling the depth of the source/drain regions. Thus typically the smaller feature size used to provide higher densities and speeds in integrated circuits requires increasingly shallow source/drain regions.
A further requirement in integrated circuit production is creation of good ohmic contacts on the source/drain regions. This may be accomplished through formation of a silicide layer on the source/drain region surfaces. In addition, the sheet resistance of the gate interconnect surfaces must be lowered to reduce RC delay across the transistor gate in high frequency circuits. This also is accomplished by formation of a silicide layer over the top surface of the gate interconnects.
Existing processes meet the above requirements through a deposition-formation step in which a single silicide layer, having a uniform thickness, is simultaneously formed on both the surfaces of the source/drain regions and the top surface of the gate interconnects. During this process, some amount of silicide forms downward and laterally through the source/drain regions. Where these source/drain regions are very shallow, and the silicide thickness is sufficiently large, the silicide may penetrate substantially or completely through the source/drain regions. Substantial penetration may result in excessive junction leakage during operation causing the device to fail.
In order to limit such junction leakage, the amount of metal deposited to form the silicide layer may be reduced, consequently reducing the amount of silicide formed. However such thinner silicide may be inadequate to meet the sheet resistance requirements of the gate interconnects. Such high sheet resistance will increase RC delay across the transistor gate thereby reducing high frequency circuit performance.
Thus it is seen that existing processes are ineffective in providing the appropriate thicknesses of silicide over both the source/drain region and gate interconnect surfaces. Therefore, a new integrated circuit fabrication process is required which allows for a sufficiently thick silicide layer over the gate interconnect areas without requiring an excessively thick silicide over the source/drain regions.